1. Field of the Invention
The present invention relates to a multiplying circuit which comprises differential amplifiers and are adapted for use in a frequency converter, a synchronous detector, a quadrature modulator, a demodulator, a variable gain amplifier, etc.
2. Description of the Related Art
Conventional multiplying circuits have two pairs of input terminals respectively supplied with two input signals to be multiplied. The input signal input to one input terminal pair is amplified by a first differential amplifier and a second differential amplifier. The output terminal pairs of the first and second differential amplifiers are connected together in such a way that the outputs of those differential amplifiers with respect to the first input signal will cancel out each other. A second input signal input to the other input terminal pair is amplified by a third differential amplifier to be converted into a change in the collector current of transistors constituting this differential amplifier.
Since the first and second differential amplifiers have their common emitter terminal connected to the collector of the collectors of the transistors of the third differential amplifier, the gains of the first and second differential amplifiers are proportional to the collector current of the transistors of the third differential amplifier. Therefore, a voltage proportional to the product of voltages of the first and second input signals or a multiplied output is yielded between the common output terminal of the first and second differential amplifiers.
Such a multiplying circuit will have a deformed output signal waveform because of the non-linearity of the differential amplifiers as the voltage amplitudes of the input signals get large. As a solution to this shortcoming there has been proposed an art of constituting the third differential amplifier with a combination of two differential amplifiers and providing the proper DC offset to these differential amplifiers to widen the linearity range as disclosed in U.S. Pat. No. 4,965,528. The DC offset of the differential amplifier is determined by the emitter area of a pair of emitter coupled transistors constituting this differential amplifier.
Another multiplying circuit has also been proposed which combines three or more differential amplifiers to constitute the third differential amplifier in order to ensure a wider linearity range. How to set a given DC off to the differential amplifiers and weight a current to each differential amplifier in this case is disclosed in Electronic Circuit Study Report No. ECT-90-20 of Electric Committee and "Realization of a 1-V Active Filter Using a Linearization Technique Employing Plurality of Emitter-Coupled Pair", IEEE JOURNAL OF SOLID-STATE CIRCUITS, pages 937-944, VOL. 26, NO. 7, JULY 1991.
In this method, however, as the number of third differential amplifiers increases, their transistors should have a larger emitter area, increasing the parasitic capacitance of the transistors so that the use of the multiplying circuit at a high frequency becomes difficult. For instance, given that the emitter area ratio of one pair of emitter coupled transistors constituting the third differential amplifier is 1:4, the sum of the parasitic capacitances present between the collectors of the emitter coupled transistors and the ground becomes about five times greater than that of the previously described conventional multiplying circuit. As the frequency of the first input signal increases, therefore, the CMRR (Common Mode Rejection Ratio) of the first and second differential amplifiers falls. In addition, the frequency rise will increase signals that leak to the second input terminal pair from the first input terminal pair through the collector-base parasitic capacitance.
The drop of the CMRR causes a local oscillator signal to the transmission output side to increase in the where the multiplying circuit is used as a frequency converter or a modulator in a transmitter, for example, with a local oscillator signal and a transmission signal respectively given as the first and second input signals to the frequency converter or the modulator. With the multiplying circuit used as a frequency converter in a receiver, for example, when the number of signals leaking to the second input terminal pair from the first input terminal pair increases, the local oscillator signal input to the first input terminal pair will increase the undesirable radiation from an antenna via the second input terminal pair, a high frequency amplifier and the like.
The conventional ways of broadening the linearity range can apply only to the third differential amplifier side to which the second input signal is to be input, and cannot widen the linearity ranges of the first and second differential amplifiers. This undesirably causes the first input signal component to be easily deformed.
If the frequencies of the first and second input signals are relatively different from that of the desired output signal as in a frequency converter or a demodulator, a multiplying circuit comprising half of the circuit components of the first described conventional multiplying circuit is often used. That is, this multiplying circuit comprises a first differential amplifier connected to a first input terminal pair, and a common-emitter transistor connected to the common emitter of the transistors of the first differential amplifier The first and second input terminal pairs of this multiplying circuit are supplied with two input signals to be multiplied, the second input terminal pair connected to the base of the common-emitter transistor. The first input signal input to the first input terminal pair is amplified by the differential amplifier, while the second input signal input to the second input terminal pair is amplified by the common-emitter transistor. A multiplied output of the first and second input signals is acquired from an output terminal provided in a load circuit of the differential amplifier.
This multiplying circuit if used as a frequency converter or a demodulator in a receiver has a disadvantage of having an insufficient noise factor. The noise generated in the multiplying circuit is mainly thermal nose from the parasitic resistor of the base of the common-emitter transistor. The thermal noise can be reduced by setting the emitter area of the common-emitter transistor larger or increasing the base area.
Increasing the emitter area of the common-emitter transistor however would result in a decrease in the CMRR of the differential amplifier and an increase in the signals leaking from the first input terminal pair to the second input terminal pair, as in the first described conventional multiplying circuit which comprises three differential amplifiers to improve the linearity. In a direct conversion type receiver, particularly, the reception frequency is nearly equal to the local oscillator frequency, so that when a local oscillator signal is input to the first input terminal pair and a reception signal to the second input terminal pair, the local oscillator signal will leak through the second input terminal pair. This gives rise to a significant problem.
In short, the first described multiplying circuit designed to improve the linearity range has the following two disadvantages:
1) The CMRR of the differential amplifier decreases in a high frequency range (radio frequency band) due to an increase in the parasitic capacitance of transistors in use and the degree of one input signal leaking from one input terminal pair to the other input terminal pair increases.
2) Widening of the linearity range is accomplished for only one of two input signals, resulting in insufficient suppression of the deformation of the other input signal.
Further, the use of a common-emitter transistor having a large emitter area to improve the nose factor in the second described conventional multiplying circuit would also result in undesirable reduction of the CMRR of the differential amplifier in a high frequency range and increase in the degree of one input signal leaking from one input terminal pair to the other input terminal pair.